1. Field of the Invention
The present invention relates to frequency divider circuits, and in particular, multiphase clock dividers for frequency dividing multiphase clock signals simultaneously.
2. Description of the Related Art
Many types of frequency dividers are well known in the art, including those that are programmable for allowing the frequency division ratio to be selected and varied. One application for frequency dividers is in digital phase lock loops where a frequency divider is often used for frequency dividing the clock signal from a reference oscillator and/or the feedback signal from the loop oscillator. A problem with such applications, however, is the effect upon the dynamic operation characteristics of the phase lock loop when a divider, and in particular, a programmable divider, is inserted within the loop. The loop dynamics change every time the frequency divider is reprogrammed. Furthermore, such effects upon the loop dynamics become even more complicated when multiphase signals must be divided.
For example, where multiphase signals are to be divided and the mutual phase relationships among the various clock phases are important, a problem which arises is that of how to frequency divide all of the phases while maintaining their mutual phase alignments and synchronization. Using a divider for each phase introduces variances among those phase relationships. Plus, depending upon the type of divider used, permanent phase errors can result if one or more of the phases experiences a "phase flip," from which it/they may never recover.
Accordingly, it would be desirable to have an improved technique for frequency dividing, and in particular, programmably frequency dividing, multiphase clock signals while maintaining the original phase alignment of the original clock signals.